`timescale 1ns / 1ps
////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:21:11 11/29/2013
// Design Name:   code_splice
// Module Name:   D:/Jayvee/H_264_Decoder/Code_Splice_Test.v
// Project Name:  H_264_Decoder
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: code_splice
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Code_Splice_Test;

	// Inputs
	reg [63:0] Code_A;
	reg [63:0] Code_B;
	reg [7:0] Bound;
    reg [7:0] cnt;
    reg Clk,Rst;
	// Outputs
	wire [63:0] Code_spliced;

	// Instantiate the Unit Under Test (UUT)
	code_splice uut (
		.Code_A(Code_A), 
		.Code_B(Code_B), 
		.Bound(Bound), 
		.Code_spliced(Code_spliced)
	);

	initial begin
		// Initialize Inputs
		Code_A = 0;
		Code_B = 64'b1111111111111111111111111111111111111111111111111111111111111111111;
		Bound = 0;
        Rst = 0;
        Clk = 0;
        cnt = 0;
		// Wait 100 ns for global reset to finish
		#100;
        #10 Rst = 1;
		// Add stimulus here

	end
    
    always #20 Clk = ~Clk;
    
    always @(posedge Clk or negedge Rst) begin
        if(!Rst) begin
            cnt <= 0;
        end
        else begin
            case(cnt)
            0:begin
                Bound <= 0;
                cnt <= cnt + 1;
            end
            1:begin
                Bound <= 1;
                cnt <= cnt + 1;
            end
            2:begin
                Bound <= 2;
                cnt <= cnt + 1;
            end
            3:begin
                Bound <= 3;
                cnt <= cnt + 1;
            end
            4:begin
                Bound <= 45;
                cnt <= cnt + 1;
            end
            5:begin
                Bound <= 64;
                cnt <= cnt + 1;
            end
            default:begin
                cnt <= 0;
            end
            endcase
        end
    end
endmodule

